1. Field of the Invention
The present invention relates to a VCD up-grading circuit board, more particularly, to a VCD up-grading circuit board, which is attached to a CD player or CD-ROM thereby allowing the CD player (CD-ROM) to be up-graded to a VCD (Video CD) player without additional connection for a synchronous clock signal.
2. Description of Related Art
A VCD (Video CD) specification for a CD has been developed to provide both visual and auditory enjoyment with high quality. The VCD specification allows compressed image signals (being compressed by a proportion 20:1 for example) in addition to stereo signals to be written into an ordinary CD. To play the data written in the CD, the compressed image signals have to be decompressed by an MPEG decompression chip or decompression software, that is, a VCD player is needed. Each CD can store about 60 minutes of images and sounds. It is clear that the VCD player, which provides both video and audio services, can substitute for a CD player and a video cassette player.
However, the CD player has become a very common audio device in homes and so it is a waste to throw away the original CD player and buy a new VCD player. Accordingly, a VCD up-grading circuit board for the CD player or CD-ROM has been designed. The VCD up-grading circuit board is installed in the CD player to allow the CD player to be up-graded to function as a VCD player being able to play both a VCD and a CD. Although the up-graded CD player can not execute a function of interactive menu of the VCD specification, the player can execute all the normal operations, such as play, stop, fast forward and reverse, via the function keys on a panel of the CD player.
A conventional VCD up-grading circuit board for a CD player is shown in FIG. 1, in which a block at the left side indicates a basic structure of a conventional CD player or CD ROM 10, and a block at the right side indicates the conventional VCD up-grading circuit board 20. As can be seen in this drawing, the CD player (or CD ROM) 10 generally comprises a CD drive 13, a CPU (central processing unit) 14, an input/display section 15, a servo CD-DSP (CD-digital signal processor) 11 and an audio DAC (digital to analog converter) 12. The conventional VCD up-grading circuit board 20 comprises an MPEG decoder 21, a DRAM (dynamic RAM) 22, an 8-bit microprocessor 23, an audio DAC 24, a TV encoder 25 and a clock generator 26. There are three data lines, which are respectively a PCM serial digital data line (PCMDATA), a serial data locking clock line (BCLK), and an L/R channel sampling clock line (LRCLK), extending from a PCM interface of the CD-DSP 11 in the CD player 10. The above three data lines are connected both to the audio DAC 12 in the CD player 10, and to the MPEG decoder 21 in the VCD up-grading circuit board 20. The PCMDATA presents the data of the left channel when the LRCLK is at high level, and presents the data of the right channel when the LRCLK is at low level. Accordingly, the data of the left channel and the data of the right channel can utilize the same data line to transmit.
The formats of the data on the three data lines may be different depends on the designs by different manufacturers. For example, FIG. 2 shows the formats of the data on the three data lines provided by SONY.TM.. Under SONY.TM. specification, the frequency of BCLK is 24 times the frequency of LRCLK in a half cycle, however, in some cases, it can be 16 or 32 times. PCMDATA is fetched and synchronized by BCLK. The frequency of LRCLK is 44.1 KHz, however, in some cases, 32 or 48 KHz. The data of the left channel and the data of the right channel are fetched by 16 bits, or 12, 18 or 20 bits in other cases, and arranged on the data line LRCLK. The 16 bits of valid data are located right before a channel switch point.
Returning to FIG. 1, in addition to the three data lines, a synchronous clock line 201 is connected between an X terminal of the servo CD-DSP 11 and an audio synchronous clock input terminal Y of the MPEG decoder 21. The synchronous clock line 201 is connected to the clock generator 26 to utilize a clock signal therefrom as a synchronous clock signal to synchronize the whole system. Digital video signals and audio signals output from the MPEG decoder 21 are synchronized by the synchronous clock signal. The DRAM 22 is used as a frame buffer for registering image frames or audio signals. The microprocessor 23 is used to control various operations and operation modes of the MPEG decoder 21, such as video output mode, PCM audio output mode and the like.
The synchronous clock signal is necessary as CD players and VCD up-grading circuit boards of different manufacturers have differences existing thereamong. Even CD players and VCD up-grading circuit boards provided by the same manufacturer may also fail to be synchronized due to inconsistency of quality. If the CD player 10 and the VCD up-grading circuit board 20 are asynchronous to each other, image errors, random codes, noises and distortion may happen since the VCD up-grading circuit board 20 cannot proceed data compression at real time.
The MPEG decoder 21 accepts data with an MPEG format only. The MPEG decoder 21 decompresses a received bit stream, which contains data being compressed according to MPEG compression format, into video signals and audio signals, wherein the audio signals are converted to analog audio signals by the audio DAC 24, and the video signals are converted to NSTC or PAL standard video signals, which can be directly played via a TV set, by the TV encoder 25. If the CD player 10 plays a CD containing only audio signals, the MPEG decoder 21 is inactive since the format of the data received from the servo CD-DSP 11 is not the MPEG format. At this time, the data is sent to the audio DAC 12 of the CD player 10 and is converted into analog audio signals to be played.
As mentioned above, the synchronous clock signal is generated by the clock generator 26 and is provided to the servo CD-DSP 11 and the MPEG decoder 21. However, the synchronous clock signal can also be provided by the servo CD-DSP 11 for the system to use, doing away with the clock generator 26. However, the following drawbacks still exist.
If the synchronous clock signal is provided from the servo CD-DSP 11 to the VCD up-grading circuit board 20, the CD player may often fail since the driving ability of the servo CD-DSP 11 is not sufficient. Alternatively, if the synchronous clock signal is generated by the clock generator 26 of the VCD up-grading circuit board 20, then an oscillator of the servo CD-DSP 11 must be removed, therefore increasing the labor and cost needed for installing the VCD up-grading circuit board 20. Moreover, the two conventional manners for providing a synchronous clock signal need an additional synchronous clock line (201) to be connected between the servo CD-DSP 11 and the MPEG decoder 21. Accordingly, there may be a problem of signal interference due to the additional connecting line.